MAX5952CUAX+【PDF 17/50 页】IC PSE CNTRLR FOR POE 36-SSOP

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High-Power, Quad, PSE Controller

for Power-Over-Ethernet

______________________________________________________________________________________ 17

A valid PD has a 25k& discovery signature characteristic

as specified in the IEEE 802.3af/at standard. Table 1

shows the IEEE 802.3af/at specification for a PSE detect-

ing a valid PD signature. See the Typical Operating

Circuits and Figure 1 (Detection, Classification, and

Power-Up Port Sequence). The MAX5952 can probe and

categorize different types of devices connected to the

port such as: a valid PD, an open circuit, a low resistive

load, a high resistive load, a high capacitive load, a posi-

tive DC supply, or a negative DC supply.

During detection, the MAX5952 keeps the external

MOSFET off and forces two probe voltages through the

DET_ input. The current through the DET_ input is mea-

sured as well as the voltage at OUT_. A two-point slope

measurement is used as specified by the IEEE 802.3af

standard to verify the device connected to the port. The

MAX5952 implements appropriate settling times and a

100ms digital integration to reject 50Hz/60Hz power-

line noise coupling.

An external diode, in series with the DET_ input,

restricts PD detection to the first quadrant as specified

by the IEEE 802.3af/at standard. To prevent damage to

non-PD devices, and to protect itself from an output

short circuit, the MAX5952 limits the current into DET_

to less than 2mA maximum during PD detection.

In midspan mode, the MAX5952 waits 2.2s before

attempting another detection cycle after every failed

detection. The first detection, however, happens imme-

diately after issuing the detection command.

High-Capacitance Detection

The CLC_EN bit in register R23h[5] enables the large

capacitor detection feature for legacy PD devices.

When CLC_EN = 1, the high-capacitance detection limit

is extended up to 100礔. CLC_EN = 0 is the default

condition for the normal capacitor size detection. See

Table 1 and the Register Map and Description section.

Table 1. PSE PI Detection Modes Electrical Requirement

(Table 33-2 of the IEEE 802.3af Standard)

PARAMETER

SYMBOL

MIN

MAX

UNITS

ADDITIONAL INFORMATION

Open-Circuit Voltage

In detection mode only

Short-Circuit Current

In detection mode only

Valid Test Voltage

VALID

2.8

Voltage Difference

Between Test Points

TEST

Time Between Any Two

Test Points

This timing implies a 500Hz maximum probing

frequency

Slew Rate

SLEW

0.1

V/祍

Accept Signature

Resistance

GOOD

26.5

Reject Signature

Resistance

BAD

< 15

> 33

Open-Circuit Resistance

OPEN

500

Accept Signature

Capacitance

GOOD

150

Reject Signature

Capacitance

BAD

礔

Signature Offset Voltage

Tolerance

2.0

Signature Offset Current

Tolerance

礎

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